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Double Ended PWM Controller
POWER MANAGEMENT Description
The SC4806 is a double ended, high speed, highly integrated PWM controller optimized for applications requiring minimum space. The device is easily configurable for current mode or voltage mode operation and contains all the control circuitry required for isolated applications, where a secondary side error amplifier is used. Designed for simplicity, the SC4806 is fully featured and requires only a few external components. It features a programmable frequency up to 1MHZ, external programmable soft start, pulse-by-pulse current limit and over current protection for both voltage and current modes, as well as a line monitoring input with hysteresis to reduce stress on the power components. A ramp pin allows for slope compensation to be programmed by external resistors for current mode. This also allows for operation in voltage mode with voltage feed forward. A unique oscillator is utilized which allows two SC4806 to be synchronized together and work out-of-phase. This feature minimizes the input and output ripples, and reduces stress and size on input/output filter components. The outputs are configured for push-pull format, dead time between the 2 outputs is programmable depending on the size of the timing components. The SC4806 features a turn on threshold of 8 volts . The device is available at a MLP-12 package.
SC4806 Multiple Function
Features
90 A starting current Pulse-by-pulse current limit for both voltage/current modes Programmable operating frequency up to 1MHz Programmable external soft start Programmable line undervoltage lockout Programmable external slope compensation Over current shutdown with separate pin Dual output drive stages on push-pull configuration Programmable mode of operation (peak current mode or voltage mode) External frequency synchronization Bi-phase mode of operation Lead free MLP-12 package,WEEE and RoHS compliant -40 to 105 C operating temperature
Applications
Telecom equipment and power supplies Networking power supplies Industrial power supplies Push-pull converter Half bridge converter Full bridge converter Isolated VRMs
Typical Application Circuit
+VIN
+
+Vo
+
-VIN
I sense
-Vo
ON/OFF
REF SYNC
Rsense
Vcc
REF
SC4806
VCC OUTA OUTB 12
3
2
1
Vcc
4 5 6
RC ILIM RAMP
LUVLO
SYNC
SS
SC1301A
GND(heatsink) GND 11 10
SC1301A
FB SC431
7
8
REF
FB
0 9
REF FB I sense
Revision: October 13, 2006
1
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SC4806
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage Supply Current SYNC, RC,RAMP, LUVLO, REF, ILM, SS to GND FB to GND REF Current OUTA/OUTB to GND OUTA/OUTB Source Current (peak) OUTA/OUTB Sink Current (peak) Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case Junction Temperature Storage Temperature Range Peak IR Reflow Temperature 10 - 40s ESD Rating (Human Body Model)
Symbol V CC ICC V FB IREF VOUTA/B Isource Isink J A J C TJ TSTG TPKG ESD
Maximum -0.5 to18 20 -0.5 to 7 -0.5 to (VREF+ 0.5) 10 -0.5 to 18 -250 250 32 3 -55 to 150 -65 to 150 260 2
Units V mA V V mA V mA mA C/W C/W C C C kV
Electrical Characteristics
Unless specified: VCC = 12V; CL = 100pF; TA = -40C to 105C
45455
Test Conditions Min Typ Max Units
Parameter VCC Supply VCC Start Threshold Hysteresis Startup Current Operating Supply Current VCC Zener Shunt Voltage PWM Maximum Duty Cycle Minimum Duty Cycle Current Sense/Limit ILM Cycle by Cycle Current Limit Threshold ILM to Output Delay ILM Auto Restart Over Current Threshold FB to RAMP Offset
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7.4 1.17 VCC < start threshold FB = 0V, RAMP = 0V IDD = 10mA 16
8 1.5
8.6 1.83 150 7
V V A mA V
Fosc = 50kHz, FB = 5V, Measured at OUTA or OUTB Fosc = 50kHz, FB = 1.5V, Measured at OUTA or OUTB
48
49
50 0
% %
450
525 50
600
mV ns
750 1.20
2
850 1.40
950 1.60
mV V
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SC4806
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VCC = 12V; CL = 100pF; TA = -40C to 105C
Parameter Line Under Voltage Lockout Start Threshold Hysteresis Soft Start Internal Soft Start Charge Current (ISS) Internal Discharge Current Oscillator Oscillator Frequency Oscillator Ramp Oscillator Fall Time RC pin to GND Capacitance Oscillator Frequency Range Sync/CLOCK Clock SYNC Threshold Sync Frequency Range B an d g ap ReferenceVoltage Reference Load Regulation Reference Line Regulation Output OUT Low Level OUT High Level Rise Time Fall Time Minimal Dead Time Thermal Shutdow n Thermal Shutdown Threshold TSD Thermal Shutdown Hysteresis
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Test Conditions
Min
Typ
Max
Unit
Rhigh = 14k, Rlow = 10k Rhigh = 14k, Rlow = 10k
-3%
VREF
5.5% of VREF
+3%
V mV
VSS = 1.5V VSS = 1.5V
25
35 10
45
A A
Rosc = 10k, Cosc = 200pF
450
500
VREF/2 +0.25
550
KHz V
Guaranteed by characterization
200 22
250
ns pF
Guaranteed by characterization
50
1000
KHz
1.75 Guaranteed by characterization FOSC *1.3
V KHz
4.75 IREF = 0 - 5mA VCC = 8.5V to 15V
5.0 10 0.3
5.25
V mV/mA mV/V
0.5 V C C = 12V Load 1nF Load 1nF 10.85 11.20 35 35 200
0.7
V V ns ns
250
ns
175 15
3
C C
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SC4806
POWER MANAGEMENT Pin Configuration
TOP VIEW
VCC OUTA OUTB
Ordering Information
DEVICE(1) SC4806MLTRT(2) PACKAGE MLPQ-12 Temp. Range (TJ) -40C to 105C
12 LUVLO SS SYNC 1 2 3 4
11
10 9 8 7 GND REF FB
Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
5
6
RC ILIM
RAMP
BOTTOM VIEW
RC ILIM RAMP
4 SYNC SS LUVLO 3 2 1 12
5
6 7 FB REF GND
GND
8 9
11
10
VCC
OUTA OUTB
(MLPQ-12 4x4)
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SC4806
POWER MANAGEMENT Pin Descriptions
LUVLO (Pin 1): Line undervoltage lockout pin. An external resistive divider from the Input supply will program the undervoltage lockout level. The external divider should be referenced to the quiet analog ground. During the LUVLO, the driver outputs are disabled. This pin can also function as an Enable/Disable. SS (Pin 2): An internal 35A current source charges the external capacitor connected to this pin. This pin is connected to one of the inputs of the PWM comparator. When the voltage on this SS pin increases, but less than 1/3 of the feedback voltage VFB, the pulse width of OUTA and OUTB gradually increases to achieve soft start. As the output voltage increases and feedback loop enters regulation, the PWM modulator is controlled by VFB. At normal operation, the voltage at SS pin is clamped at Vref. When the Over Current is tripped, both OUTA and OUTB are pulled low after a typical time delay (Typ. 100ns). At the same time, the SS cap is gradually discharged via an equivalent 10A internal current source. When the voltage on SS pin is dropped below 0.8V, a new SS cycle is initiated while the SS cap is charged with 35A again. The internal thermal protection circuit monitors the die temperature. If the temperature exceeds 175oC, the controller is completely shutdown. When the temperature is dropped below 160oC, defined by the hysteresis, the controller re-starts with soft start process. SYNC (Pin 3): SYNC is a positive edge triggered input with a threshold set to 1.75V. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock within the SYNC frequency range. In Bi-Phase operation mode SYNC pins could be connected to the Cosc (Timing Capacitors) of the other controller. This will force an out-of-phase operation (see Application Information part). RC (Pin 4): The oscillator programming pin. The oscillator should be referenced to a stable reference voltage for an accurate and stable frequency. Only two components are required to program the oscillator, a resistor (tied to Vref and RC), and a capacitor (tied to the RC and GND). The following formula can be used for a close approximation of the oscillator frequency.
FOSC 1 R OSCCTOT
where:
CTOT = COSC + CSC4806 + CCircuit CSC4806 22pF
The recommended range of timing resistors is between 10kohm and 200kohm and range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10kohm should be avoided. Refer to layout guidelines in Application Information section to achieve best results. ILim (Pin 5): The current signal from a sense resistor is applied to peak current and overcurrent comparators through ILM pin. Under normal operation condition, the comparators are not trigged. When the current signal sensed at ILM pin exceeds the first threshold -- pulse-by-pulse current limit, the corresponding on-time is terminated for the remainder of the switching cycle. In this case, the circuit output voltage loses regulation even though it continues to provide full load current. When the load current continuously increases and the sensed signal at ILM pin reaches the second threshold - over current limit, the controller turns off both OUTA and OUTB. At the same time, the SS cap is discharged with equivalent 10uA current source. When the voltage at SS pin is below 0.5V, the controller initiates re-start. The pins Ramp and ILM are discharged by the internal FETs at the end of each switching cycle.
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SC4806
POWER MANAGEMENT Pin Descriptions (Cont.)
Ramp (Pin 6): The signal at this pin will be used as the PWM ramp signal that will be compared to the FB to achieve regulation. The modes of operation can be programmed depending on how this pin is configured (For more details see Application section). For voltage mode control, the PWM ramp is generated via external RC circuit connected from a voltage source to the Ramp pin. Connection to a fixed voltage source (REF) will provide a constant peak ramp with a frequency set by the internal oscillator frequency programed at the RC pin. Connection to a variable source such as the VIN will provide the added benefit of the feed forward function enhancing the converter static and dynamic performance. For Current mode control the current information from the ILim pin can be directly connected to the Ramp pin without the need for the external RC circuit at the Ramp pin. If current mode of operation with slope compensation is required, an external resistor connected from the ILim pin to the Ramp pin will provide the slope compensation. The percentage of the slope compensation will be inversely proportional to the value of the resistor ( the higher resistor lower slope compensation, the lower resistor higher slope compensation). 1/3 of external feedback signal to FB pin by an internal 3 to 1 resistor divider compares to the combined current signal to generate PWM control signal. FB (Pin 7): The inverting input to the PWM comparator through an internal 3 to 1 resistor divider. Stray inductances and parasitic capacitance should be minimized by utilizing ground planes and correct layout guidelines. REF (Pin 8): Bandgap reference output. It is recommended by placing a minimum 2.2uF low ESR capacitor right at the pin. GND (Pin 9): Device power and analog ground. The exposed paddle area on the back of the package must be connected to the GND (pin9). Careful attention should be paid to the layout of the ground planes. OUTB (Pin 10) and OUTA (Pin 11): Out of phase gate drive stages. The driver's peak source and sink current drive capability of 100mA, enables the use of an external MOSFET driver or a NPN/PNP transistor totem pole driver. The oscillator RC network programs the oscillator frequency, which is twice the OUTA/OUTB frequency. To insure that the outputs do not overlap, a dead time can be generated between the two outputs by sizing the oscillator timing capacitor (see Application Information section). VCC (Pin 12): The supply input for the device. Once VCC has exceeded the UVLO limit, the internal reference, oscillator, drivers and logic are powered up. A low ESR capacitor, should be placed right at the pin to minimize noise problems. It is recommended that the VCC rising rate during start-up be smaller than 10V/mS. THERMAL PAD: Pad for heatsinking purposes. Connect to ground plane using multiple thermal vias. Not connected internally.
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SC4806
POWER MANAGEMENT Block Diagram
RAMP
35uA
10uA
ABOA
Marking Information
Top View
yyww = Date Code (Example: 0012) xxxxxx = Semtech Lot #
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SC4806
POWER MANAGEMENT Application Information
SC4806 is a versatile double ended, high speed, low power, pulse width modulator optimized for applications requiring minimum space. The device contains all of control and drive circuity required for isolated or non isolated power supplies where an external error amplifier is used. A fixed oscillator frequency (up to 1MHz) can be programmed by an external RC network. SC4806 is a peak current or voltage mode controller, depending on the amount of slope compensation, programmable with only one external resistor. The cycle by cycle peak current limit prevents core saturation when a transformer is used for isolation while the auto-restart over-current circuitry initiates the soft-start cycle. SC4806 dual output drive stages are arranged for double ended configurations. Both outputs switch at half the oscillator frequency using a toggle flip flop. The dead time between the two outputs is programmable depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. SC4806 also provides flexibility with programmable LUVLO thresholds, with built-in hysteresis. POWER SUPPLY POWER SUPPLY A single supply, VCC is used to provide the bias for the internal reference, oscillator, drivers, and logic circuitry of SC4806. PWM CONTROLLER SC4806 is a double ended PWM controller that can be used in voltage or current mode applications. The oscillator frequency is programmed by a resistor and a capacitor network connected to an external reference provided by the SC4806. The two outputs, OUTA and OUTB, are 180 degrees out-of-phase and run at half of the oscillator frequency. An external error amplifier will provide the error signal to the FB pin of the SC4806. The current limit input and external slope compensation are provided separately via the ILIM and RAMP pins. The current limit signal from a sense resistor or a current sense transformer is used for the peak current and auto-restart overcurrent comparators.
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To generate PWM control signal, 1/3 of external feedback signal to FB pin by an internal 3 to 1 resistor divider compares to the combined current signal if an external resistor is connected from ILIM to RAMP. The value of the resistor will determine the level of slope compensation. The slope signal to RAMP is generated from either input voltage or VREF with external RC. Voltage mode of operation can be achieved if the slope signal is only used. Two levels of undervoltage lockout are also available. The LUVLO (line under voltage lockout) pin via an external resistive divider programs input voltage turn-on level. During the LUVLO, the driver outputs are disabled and the soft-start is reset. The VCC UVLO (under voltage lockout) determines VCC voltage turn-on level. Once VCC exceeds the UVLO limit, the internal reference, oscillator, drivers and logic are powered up. SYNC is a positive edge triggered input with a threshold set to 1.75V. By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range. In the Bi-phase operation mode, a very unique oscillator is utilized to allow two SC4806s to be synchronized together and work out of phase. This feature is set up by simple connection of the SYNC input of one part to the RC pin of the other. The master oscillator forces the two PWMs to operate out of phase. This feature minimizes the input and output ripples, and may reduce input and output capacitors. VCC UNDER VOLTAGE LOCK OUT VOL OLT LOCK CC Depending on the application and the voltages available, the SC4806 (UVLO = 8V) can be used to provide the VCC undervoltage lock out function to ensure the converters controlled start up. Before the VCC UVLO has been reached, the internal reference, oscillator, OUTA/OUTB drivers, and logic are disabled. VOL OLT LOCK LINE UNDER VOLTAGE LOCK OUT The SC4806 also provides a line undervoltage (LUVLO = Vref) function. The LUVLO pin is programmed via an exwww.semtech.com
SC4806
POWER MANAGEMENT Application Information (Cont.)
ternal resistor divider connected as shown below. The actual start-up voltage can be calculated by using the equation below:
V Startup = V REF R1 ) x (1 + R2
The oscillator has a ramp voltage of about Vref/2. The oscillator frequency is twice the frequency of the OUTA and OUTB gate drive controls. The oscillator capacitor CT is charged from the Vref through RT. Once the RC pin reaches about Vref/2, the capacitor is discharged internally by the SC4806. It should be noted that larger capacitor values will result in a longer dead time during the down slope of the ramp. The following equation can be used as an approximation of the oscillator frequency and the Dead time:
FOSC 1 R OSC C TOT
+VIN
+
-VIN
R1
ON/OFF
REF SYNC
R2
where:
SC4806
VCC OUTA OUTB 12 11 10
Vcc
4 5 6
RC ILim RAMP
LUVLO
SYNC
C TOT = C OSC + C SC4806 + C Circuit CSC4806 22pF
Tdeadtime C OSC x VREF x 0.5 3 10 - 3
2 SS 8 REF
3
7
0 9
GND(heatsink) GND
FB
1
REF FB I sense
REFERENCE A 5V reference voltage is available that can be used to source a typical current of 5mA to the external circuitry. The Vref can be used to provide the oscillator RC network with a regulated bias. OSCILLATOR OSCILLATOR The oscillator frequency is set by connecting a RC network as shown below.
+VIN
The recommended range of timing resistors is between 10 kohm and 200kohm, range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. SYNC/Bi-Phase operation In noise sensitive applications where synchronization of the oscillator frequency to a reference frequency may be required, the SYNC pin can accept the external clock. By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. SYNC is a positive edge triggered input with a threshold set to 1.75V. In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range.
REF
SYNC
SC4806
VCC OUTA OUTB 12 11 10
Vcc
RT 4 CT 5 6 RC ILIM RAMP
REF FB I sense
In the Bi-phase operation mode a very unique oscillator is utilized to allow two SC4806's to be synchronized together and work out of phase. This feature is set up by a simple connection of the SYNC input to the RC pin of the other part. The master oscillator forces two PWMs to operate out of phase. This feature minimizes the input and output ripples, and may reduce input and output capacitors.
3
2
7
8
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0 9
GND(heatsink) GND
REF
FB
LUVLO
SYNC
SS
1
9
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SC4806
POWER MANAGEMENT Application Information (Cont.)
REF
1
3
2
3
Vcc
VCC OUTA OUTB 12 11 10
2
1
S lave S C 4806
4 Cosc1 5 6 RC ILIM
REF
M aster S C 4806
4 Cosc2 5 6 RC ILIM
Vcc
VCC OUTA OUTB 12 11 10
SS
SYNC
LUVLO
SYNC
SS
GND(heatsink) GND
RAMP REF FB
RAMP REF FB
GND(heatsink) GND
LUVLO
Rosc1
Rosc2
The signal at the FB pin is then compared to the 3X signal from the current sense/ slope compensation RAMP pin. Matched out of phase signals are generated to control the OUTA and OUTB gate drives of the two phases. A single ramp signal is used to generate the control signals for both phases, hence achieving a tightly matched per phase operation. Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to provide enough head room for the opto coupler used in isolated applications. GATE DRIVERS
7
8
0 9
7
8
OUTA (PWM1)
0 9
OUTB (PWM1)
OUTA (PWM2)
OUTB (PWM2)
FEED BACK The error signal from output of an external error amplifier such as SC431 or SC4431 is applied to the inverting input of the PWM comparator at the FB pin either directly or via an opto-coupler for the isolated applications. For best stability, keep the FB trace length as short as possible.
+Vo
Lo1 + Co1
OUTA and OUTB are out of phase bipolar gate drive output stages, that are supplied from VCC and provide a peak source/sink current of about 100mA. Both stages are capable of driving the logic input of external MOSFET drivers or a NPN/PNP transistor buffer. The output stages switch at half the oscillator frequency. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This "dead time" between the two outputs, along with a slower output rise and fall time, insures that the two outputs can not be on at the same time. The dead time is programmable and depends upon the timing capacitor. It should be noted that if high speed/high current drivers such as the SC1301 are used, careful layout guide lines must be followed in order to minimize stray inductance, which might cause negative voltages at the output of the drivers. This negative voltage can be clamped to a reasonable level by placing a small Schottky diode directly at the output of the driver as shown below:
VCC
-Vo
S C 4 80 6
3 2 1 SS 1
3 5
D_B1
4 Gate_A
REF
LUVLO
SYNC
D_B2
VCC OUTA OUTB 12 11 10 VCC 2
4 5 6
RC ILIM RAMP
SC1301A
FB
7
8
0 9
GND(heatsink) GND
REF
FB
3 5
D_A1
SC431
1
4
Gate_B
D_A2
2
SC1301A
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SC4806
POWER MANAGEMENT Application Information (Cont.)
OPERATION OPERATION MODE SC4806 can be configured in either voltage mode or current mode. In voltage mode, a ramp is externally generated by RC network. The R can be connected to Vref or other fixed voltage source as shown below. By comparing control signal to the ramp, PWM duty cycle is derived. In current mode control, the ramp voltage is not derived artificially from a ramp generator. It is instead provided from a power converter inductor current by a current sensing transformer or resistor. Thus a second, inner control loop is formed by comparing the inductor current ramp to control voltage from outer voltage loop. Now the control voltage programs the inductor current via the inner loop and no longer controls the duty cycle directly. The current mode control corrects most of problems with direct duty cycle control in voltage mode. The chief advantage of the methods its inherent feed-forward characteristics and simplified loop dynamics. An added benefits is the reduction or elimination of transformer saturation problems in full-bridge or push-pull isolated converters. The current mode configuration with SC4806 is as shown below:
SC4806 100% Current mode (No Slope Compensation)
R3
SC4806 Voltage mode (Non-Feed Forward)
Vref or other fixed Voltage source
R1
Ramp
C1
Isense
C2
ILIM
Ramp
R3
Isense
ILIM
C2
Voltage mode with feed-forward operation is implemented if the R is connected to input voltage as shown below. With this implementation, the ramp amplitude varies directly with input voltage. If control signal to FB is constant, the duty cycle varies inversely with input voltage. Thus the volt-second product, Vin*D, remains constant without any control change. Open loop line regulation better than direct duty cycle control as shown above. Good dynamic response is achieved with less closed loop gain required.
SC4806 Voltage mode (Feed Forward)
Vin
The current mode control ling the peak inductor current results in circuit instability whenever the steady state duty cycle is greater than 0.5. An artificial slope has to be added to avoid such problem. Power transformer magnetizing current riding on the reflected inductor current acts to provide some slope compensation, but the amount is rather variable and indeterminate. The current mode with slope compensation is as shown below:
SC4806 Current mode (With Slope Compensation)
Vref or other fixed Voltage source
R1
Ramp
C1
RC
Ramp
R3
Isense
C2
ILIM
ILIM
Isense
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SC4806
POWER MANAGEMENT Application Information (Cont.)
ST SOFT S TART During start up of the converter, the discharged output capacitor and the load current have large supply current requirements. To avoid this a soft start scheme is usually implemented where the duty cycle of the regulator is gradually increased from 0% until the soft start duration is elapsed. SC4806 has soft start circuit with an external capacitor that limits the duty cycle for a duration approximated by the formula below. Also the soft start circuitry is activated if an over current condition occurs. After an over current condition, OUTA and OUTB are disabled and kept low. After the delay, the OUTA and OUTB are enabled while the soft start limits the duty cycle. If the over current condition persists, the soft start cycle repeats indefinitely. START UP SEQUENCE Initially during the power up, the SC4806 is in under voltage lock out condition. As the Vcc supply exceeds the UVLO limit of the SC4806, the internal reference, oscillator, and logic circuitry are powered up. The OUTA and OUTB drivers are not enabled until the line under voltage lock out limit is reached. At that point, once the FB pin is above 1.5V, soft start circuitry starts the output drivers, and gradually increases the duty cycle from 0%. As the output voltage starts to increase, the error signal from the error amplifier starts to decrease. If isolation is required, the error amplifier output can drive the LED of the opto isolator. The output of the opto is connected in a common emitter configuration with a pull-up resistor to a reference voltage connected to the FB pin of the SC4806. The voltage level at the FB pin provides the duty cycle necessary to achieve regulation. If an over current condition occurs, the outputs are disabled and after a soft start delay time of about 100s, the soft-start sequence mentioned above is repeated.
LAY LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC4806 PWM controller. High current switching is present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1) The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, such as the input capacitor and FET ground. 2) In the loop formed by the Input Capacitor(s) (Cin), the FET must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) The connection between FETs and the Transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) A SC4806 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VCC supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. Avoid making a star connection be-
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SC4806
POWER MANAGEMENT Application Information (Cont.)
tween the quiet GND planes that the SC4806 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible The GND connections should be connected to the quiet GND used for the SC4806. 7) If an Opto isolator is used for isolation, quiet primary and secondary ground planes should be used. The same precautions should be followed for the primary GND plane as mentioned in item 5 mentioned above. For the secondary GND plane, the GND plane method mentioned in item 4 should be followed. 8) All the noise sensitive components such as LUVLO resistive divider, reference by pass capacitor, Vcc bypass capacitor, current sensing circuitry, feedback circuitry, and the oscillator resistor/capacitor network should be connected as close as possible to the SC4806. The GND return should be connected to the quiet SC4806 GND plane. 9) The connection from the OUTA and OUTB of the SC4806 should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints, a small Schottky diode may be connected from the OUTA/B pins to the ground directly at the IC. This will clamp excessive negative voltages at the IC. If drivers are used, the Schottky diodes should be connected directly at the IC from the output of the driver to the driver ground. 10) If the SYNC function is not used, the SYNC pin should be grounded at the SC4806 GND to avoid noise pick up.
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SC4806
CON2 9 Vout+
JP3 2 Vin+ 4 3 CON1 C8 1u,100V C9 1u,100V C10 1u,100V Vin+ FZT853 Q2 B C 8 VCC E 1 49.9k R8 R9 250 JP1 JP2 JP6 5 1
PA0810 11
6T 1T
JP9 10 10 8 JP11 JP12
6T 1T
MBRB2535CTL 1 4 3 R14 D1 2.2n C13 1 10 JP10 7 R16 2.2n C15 MBRB2535CTL 1 4 3
4T
R13
8 L1 2 C16 22u,6.3V C17 22u,6.3V 0.9uH
0
Sens
C18 22u,6.3V
C19 22u,6.3V
C20 22u,6.3V
C21 22u,6.3V
C14 0.1u
C22 0.1u
7
Trim
7
D2 6 T1 R18 4 3 T3 P8208T 16.2
0
R20
R42 TBD
6
ON/OFF
2
0
Sens
VCC = 12V
D4 ZM4743A C C11 .1u,16V C12 10u,16V Vin3 MA1 SUD19N20-90 0 1 R_GS_MA1 10k 2 2.2 R19 0 R21 56.2k JP5 JP4 JP8 JP7 VCC R17 2.2 100p C23 R11 10k 100 R15 0 1 R_GS_MB1 100p C7 2 A 4
5 3 100 R10
Vout-
N = 100
MB1 SUD19N20-90
U2 RH02 1 3
5output_half _brick
2 1 L2 R12 0
1
C24
2
10u,16V
G_A LUVLO & ON/OFF & OVP J1 C25 1nF SS J2 C26 0.1uF 16V VCC VCC J3 REF JP25 SYNC 0.1u,25V C29 3 2 R25 15k SS LUVLO SYNC 4 RC GND(heatsink) GND ILim RAMP OUTB REF FB 10 VCC OUTA 11 VCC C30 82pF ILim 5 6 R_Pull_Up 3.01k 12 1 G_A G_A_cap R22 10k
G_B
CMOSH-3
C
3 5
R23 TBD D7 AC 1 4 C28 22nF R26 C CMOSH-3 C A D8 A 2 CMOSH-3
U1 SC4806
R24 10
C27 0.1u
U3 SC1301A
G_B
T4 1 6
CMOSH-3
0
D10 D9 A 1u,16V C31
Sy nc Driv e Supply Sy nc Driv e Supply R28 PE-68386 J4 J5 C33 0.1u AC 1 4 CMOSH-3 C 3 5
0
R31
D11 D12 A
CMOSH-3
3
4
CMOSH-3 C A
C
2.2k
POWER MANAGEMENT Push Pull Evaluation Board Sch
R_Slope_V 7 REF 8 0 9 20k Q_Slope_Comp 301
R_Slope_I
U5 SC4431
D13 0 U7 D14 CMOSH-3 8 REF J7 7 2 1 C34 0.1u C35 22n
1
5
R30 37.4k
4
C36 2.2u,16V
J6
A
2
U6 SC1301A
ILim_in 1k R1 82p C2 C 15 R4 LS4448 A D3 10k R3 JP28
R33 1k 6 5 MOCD207 2.2k 3 4 R37
Sy nc Driv e Supply
2
Vref
FMMT718
R32 18.2k
C37 .1uF
100pF C40
C41
R38
R36 11.5k
1nF
15k
1
5 C43 0.1u R43 100 C C44 22n
R39 25.5k
C42 470pF
4
U8 SC4431
D15 1N5819HW A
Vref
R41 15k
2006 Semtech Corp.
2
14
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SC4806
POWER MANAGEMENT Evaluation Board Bill of Materials
SC4806 Slope Compensation Current Mode Push Pull 3.3V 35W non Synchronous SC4806EVB__non_sync Revision: 1.1 Bill Of Materials Item Quantity
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 1 1 1 2 3 1 2 2 6 6 2 1 1 1 1 1 2 1 1 1 1 2 1 1 8 8 1 14 1 1 1 1 1 1 1 1 1 2 1 1 3 1 1 1 2 1 1 1 2 2 2 1 1 1 2 1 3 2 1 1 1 1 1 1 1 1 1 1 2 2 1
March 30,2005 Reference
11:27:17 Part
3input_half_brick 5output_half_brick 82p 100p 1u,100V .1u,16V 10u,16V 2.2n 0.1u 22u,6.3V 1nF 0.1uF 16V 22nF 0.1u,25V 82pF 1u,16V 22n 2.2u,16V .1uF 100pF 470pF MBRB2535CTL LS4448 ZM4743A 0 CMOSH-3 1N5819HW short SS Vcc SYNC OUTA OUTB REF FB 0.9uH LQH43MN102K011 SUD19N20-90 FMMT718 FZT853 10k 3.01k 301 20k 1k 15 49.9k 250 100 2.2 10 16.2 56.2k 10k TBD 10 15k 2.2k 37.4k 18.2k 11.5k 25.5k 100 PA0810 P8208T PE-68386 SC4806 RH02 SC1301A SC4431 MOCD207 CMOSH-3 (Central Semiconductor)
Manufacturer #
Foot Print
CON\3INPUT_HALF_BRICK CON\5OUTPUT_HALF_BRICK SM/C_0805 SM/C_1206 SM/C_2220 SM/C_0805 SM/C_1210_GRM SM/C_1206 SM/C_0805 SM/C_1210_GRM SM/C_0805 SM/C_0603 SM/C_1206 SM/C_1206 SM/C_0805 SM/C_1210_GRM SM/C_0805 SM/C_1206 SM/C_0805 SM/C_0805 SM/C_0805 DIODE_D2PAK SM/DO213AC SMB/DO214 SM/R_0805 SOD523 SOD123 VIA\2P ED5052 ED5052 ED5052 ED5052 ED5052 ED5052 ED5052 PG0006 SDIP0302 DPAKFET SM/SOT23_BEC SM/SOT223_BCEC SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_1206 SM/R_1210_MCR SM/R_1206 SM/R_0805 SM/R_1206 SM/R_0805 SM/R_1206 SM/R_1206 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 PA0810 P8208T PE-68386 MLPQ-12 (4X4) RH02 SOT23_5PIN SOT23_5PIN SO-8
CON1 CON2 C2 C23,C7 C8,C9,C10 C11 C24,C12 C13,C15 C14,C22,C27,C33,C34,C43 C16,C17,C18,C19,C20,C21 C41,C25 C26 C28 C29 C30 C31 C44,C35 C36 C37 C40 C42 D2,D1 D3 D4 D5,D6,R12,R13,R19,R20, R26,R31 D7,D8,D9,D10,D11,D12,D13, D14 D15 JP1,JP2,JP3,JP4,JP5,JP6, JP7,JP8,JP9,JP10,JP11, JP12,JP25,JP28 J1 J2 J3 J4 J5 J6 J7 L1 L2 MB1,MA1 Q_Slope_Comp Q2 R_GS_MB1,R_GS_MA1,R3 R_Pull_Up R_Slope_I R_Slope_V R1,R33 R4 R8 R9 R10,R15 R17,R11 R16,R14 R18 R21 R22 R42,R23 R24 R25,R38,R41 R37,R28 R30 R32 R36 R39 R43 T1 T3 T4 U1 U2 U6,U3 U5,U8 U7
GRM44-1X7R105K250AL(muRata) GRM32DR61C106KA01(muRata)
GRM32DR60J226KA01(muRata)
GRM32RR71H105KA011(muRata)
PG0006.102(Pulse) LQH43MN102K01L(muRata) SUD19N20-90(vishay) FMMT718 (Zetex) FZT853 (Zetex)
PA0810(Pulse) P8208T(Pulse) PE-68386(Pulse) SC4806(Semtech) RH02(Diodes Inc.) SC1301A(Semtech) SC4431(Semtech)
2006 Semtech Corp.
15
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SC4806
POWER MANAGEMENT Evaluation Board Gerber Plots
Board Layout Assembly TOP
Board Layout Assembly Bottom
2
1
Board Layout Top
2006 Semtech Corp. 16
Board Layout Bottom
www.semtech.com
SC4806
POWER MANAGEMENT Evaluation Board Gerber Plots (Cont.)
Board Layout Inner1
Board Layout Inner2
Evaluation Board Modifications
1
R Slope I
Q Slope Comp
D15
R43
R Pull up
R Slope V
2
Board Layout Bottom
2006 Semtech Corp. 17 www.semtech.com
SC4806
Vin+ JP17
CON1 C8 1u,100V C9 1u,100V FZT853 Q2 B MB1 SUD19N20-90 C4 2.2u,50V 2.2 0 1 R_GS_MB1 10k 2 JP19 JP18 JP20 4 3
1T
R8 C10 1u,100V 3 1 49.9k C 100 R10 100p C7 2
4T
R9 250
Vin+
CON2 9 Vout
N/OFF
2 E
VCC R11 0 R12
PA0801
1T 1T
11 10
JP22 10 JP24 9 8 R14 2.2n C13 10 R16
4
MBRB2535CTL 1 3 D1 1 MBRB2535CTL 1 1.9uH L1 2 C16 47u,6.3V C17 47u,6.3V C18 47u,6.3V
R13
VCC = 12V
D4 ZM4743A C C11 .1u,16V 4 A C12 10u,16V
8
0
Sens
C19 47u,6.3V
C20 47u,6.3V
C21 47u,6.3V
C14 0.1u
Vin-
JP21 5 1 C6 2.2u,50V MA1 SUD19N20-90 8 0 1 R_GS_MA1 10k 2 100p C23 100 R15 7 3
4T 1T
C22 0.1u
JP23 7
7 2.2n C15 4 3
4T
Trim
D2 6 T1 R18 4 3
0
R20
R42 TBD
6
0
Sens
R17 2.2 R19 0 JP15 R21 56.2k C1 2.2n 2 5 4 3 10 2.2n 10 R6 C5 R7 JP16 JP13 JP14
T3 P8208T
16.2
5
Vout-
N = 100
U2 RH02 1 3
5output_half _brick
2 1 L2
1
C24
2
10u,16V
VCC T2 PA0264 G_A_cap 1 LUVLO & ON/OFF & OVP J1 C25 1nF SS C26 0.1uF 16V VCC VCC CMOSH-3 G_A J3 Vin+ JP25 SYNC 0.1u,25V C29 AC 1 4 3 2 R25 15k SS LUVLO SYNC 4 RC GND(heatsink) GND ILim RAMP OUTB REF FB 10 OUTA 11 VCC C30 82pF ILim 5 6 C32 82pF 12 2 1 REF C 3 5 J2 R22 10k
6
G_B
R23 TBD C28 22nF
U1 SC4806
A
R24 10
C27 0.1u
D7
C
CMOSH-3 C A
JP26
D8
CMOSH-3
R26
R27 316k
U3 SC1301A
VCC G_B CMOSH-3
1
T4
CMOSH-3
0 6
D9 A 1u,16V C31
D10
Sy nc Driv e Supply Sy nc Driv e Supply R28 PE-68386
0
C R31 3 5 C33 0.1u
D11
CMOSH-3
3
4
CMOSH-3 C A
C
1
D12 A
2.2k 5 1 4 D13 AC 0 CMOSH-3 8 D14 REF J7 A 2 7 U7 1 2 C34 0.1u C35 22n
U5 SC4431
POWER MANAGEMENT HB Evaluation Board Schematics
REF 8
J4
J5
R30 37.4k
7
0 9
C36 2.2u,16V
4
J6
U6 SC1301A
ILim_in 1k R1 82p C2 1 15 R4 2 RH02 U4
R33 1.1k
6 5 MOCD207 4 3
3 4
C39 6.8nF
R35 0 R37 1.1k 5 C43 0.1u R43 100 C C44 22n
Sy nc Driv e Supply
2
Vref
R32 18.2k
C37 .1uF
47pF
C40
C41
R38
R36 1.62k
2.2nF
25.5k
1
R39 25.5k
C42 680pF
4
U8 SC4431
D15 1N5819HW A
2
Vref
R41 15k
2006 Semtech Corp.
18
www.semtech.com
SC4806
POWER MANAGEMENT Evaluation Board Bill of Materials
SC4806 Feed Forward Half bridge 3.3V 35W non Synchronous SC4806EVB__non_sync Revision: 1.1 Bill Of Materials Item Quantity
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 1 1 2 1 2 2 3 1 2 2 6 6 1 1 1 1 2 1 2 1 1 1 1 1 1 2 1 8 8 1 14 1 1 1 1 1 1 1 1 1 2 1 2 1 1 3 1 1 2 2 2 1 1 1 2 2 1 1 1 1 2 1 1 2 1 1 1 1 1 1 2 2 2 1
March 30,2005 Reference
10:47:27 Part
3input_half_brick 5output_half_brick 2.2n 82p 2.2u,50V 100p 1u,100V .1u,16V 10u,16V 2.2n 0.1u 47u,6.3V 1nF 0.1uF 16V 22nF 0.1u,25V 82pF 1u,16V 22n 2.2u,16V .1uF 6.8nF 47pF 2.2nF 680pF MBRB2535CTL ZM4743A 0 CMOSH-3 1N5819HW short SS Vcc SYNC OUTA OUTB REF FB 1.9uH LQH43MN102K011 SUD19N20-90 FZT853 10k 1k 15 10 49.9k 250 100 2.2 10 16.2 56.2k 10k TBD 15k 316k 2.2k 37.4k 18.2k 1.1k 0 1.62k 25.5k 100 PA0801 PA0264 P8208T PE-68386 SC4806 RH02 SC1301A SC4431 MOCD207 CMOSH-3 (Central Semiconductor)
Manufacturer #
Foot Print
CON\3INPUT_HALF_BRICK CON\5OUTPUT_HALF_BRICK SM/C_0805 SM/C_0805 SM/C_2220 SM/C_1206 SM/C_2220 SM/C_0805 SM/C_1210_GRM SM/C_1206 SM/C_0805 SM/C_1210_GRM SM/C_0805 SM/C_0603 SM/C_1206 SM/C_1206 SM/C_0805 SM/C_1210_GRM SM/C_0805 SM/C_1206 SM/C_0805 SM/C_0603 SM/C_0805 SM/C_0805 SM/C_0805 DIODE_D2PAK SMB/DO214 SM/R_0805 SOD523 SOD123 VIA\2P ED5052 ED5052 ED5052 ED5052 ED5052 ED5052 ED5052 PG0006 SDIP0302 DPAKFET SM/SOT223_BCEC SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_1206 SM/R_1210_MCR SM/R_1206 SM/R_0805 SM/R_1206 SM/R_0805 SM/R_1206 SM/R_1206 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0603 SM/R_0805 SM/R_0805 SM/R_0805 PA0805 PE-68386 P8208T PE-68386 MLPQ-12 (4X4) RH02 SOT23_5PIN SOT23_5PIN SO-8
CON1 CON2 C1,C5 C2 C4,C6 C23,C7 C8,C9,C10 C11 C12,C24 C15,C13 C14,C22,C27,C33,C34,C43 C16,C17,C18,C19,C20,C21 C25 C26 C28 C29 C32,C30 C31 C44,C35 C36 C37 C39 C40 C41 C42 D1,D2 D4 D5,D6,R12,R13,R19,R20, R26,R31 D7,D8,D9,D10,D11,D12,D13, D14 D15 JP13,JP14,JP15,JP16,JP17, JP18,JP19,JP20,JP21,JP22, JP23,JP24,JP25,JP26 J1 J2 J3 J4 J5 J6 J7 L1 L2 MB1,MA1 Q2 R_GS_MB1,R_GS_MA1 R1 R4 R6,R7,R24 R8 R9 R15,R10 R17,R11 R16,R14 R18 R21 R22 R23,R42 R41,R25 R27 R28 R30 R32 R33,R37 R35 R36 R39,R38 R43 T1 T2 T3 T4 U1 U4,U2 U6,U3 U5,U8 U7
GRM44-1X7R105K250AL(muRata) GRM32DR61C106KA01(muRata)
GRM43-2X5R476K6.3(muRata)
GRM32RR71H105KA011(muRata)
PG0006.212(Pulse) LQH43MN102K01L(muRata) SUD19N20-90(vishay) FZT853 (Zetex)
PA0801(Pulse) PA0264 (Pulse) P8208T(Pulse) PE-68386(Pulse) SC4806(Semtech) RH02(Diodes Inc.) SC1301A(Semtech) SC4431(Semtech)
2006 Semtech Corp.
19
www.semtech.com
SC4806
POWER MANAGEMENT Evaluation Board Gerber Plots
Board Layout Assembly TOP
Board Layout Assembly Bottom
2
Board Layout Top
2006 Semtech Corp. 20
Board Layout Bottom
www.semtech.com
SC4806
POWER MANAGEMENT Evaluation Board Gerber Plots (Cont.)
Board Layout Inner1
Board Layout Inner2
Evaluation Board Modifications
D15
R43
2
Board Layout Bottom
2006 Semtech Corp. 21 www.semtech.com
SC4806
POWER MANAGEMENT Outline Drawing - MLPQ-12, 4 x 4
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
A
D
B
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.031 .040 .002 .000 (.008) .010 .012 .014 .153 .157 .161 .074 .085 .089 .153 .157 .161 .074 .085 .089 .031 BSC .018 .022 .026 12 .003 .004 0.80 1.00 0.05 0.00 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 1.90 2.15 2.25 3.90 4.00 4.10 1.90 2.15 2.25 0.80 BSC 0.45 0.55 0.65 12 0.08 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 LxN E/2 E1 2 1 N e D/2
NOTES: 1. 2.
SEATING PLANE C
bxN bbb
CAB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ-12, 4 x 4
K
DIM
2x (C) H 2x G 2x Z C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.148) .106 .091 .091 .031 .016 .041 .189 (3.75) 2.70 2.30 2.30 0.80 0.40 1.05 4.80
Y X P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp. 22 www.semtech.com

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